1. Field of the Invention
The present invention relates to floating point units and, more particularly, but not by way of limitation, to a method and apparatus for detecting underflow and overflow.
2. Description of the Related Art
When implementing the ANSI/IEEE standard 754-1985, typical floating point units include circuits configured such that they sequentially: 1) perform a desired arithmetic operation on a first and second operand, 2) normalize the mantissa of the result, 3) adjust the exponent of the result, 4) determine if an underflow or overflow will occur due to the adjustment of the exponent, and 5) if no underflow or overflow will occur, modify both the mantissa and exponent to produce a floating point number conforming to the IEEE standard.
The normalization circuitry typically includes a shift register that shifts the mantissa resulting from the arithmetic operation either left or right within the mantissa bit field until the bit to the left of the decimal point is non-zero. Each shift of the mantissa to the left requires the exponent to decrease by a value of one. Conversely, each shift of the mantissa to the right requires the exponent to increase by a value of one. Additionally, the shift register calculates an offset amount associated with the shift value.
The exponent adjustment circuitry includes an arithmetic logic unit (ALU) that inputs an exponent from one of the operands and the offset determined by the normalize circuitry to adjust the exponent for the answer. Thus, the exponent of the operand input into the ALU provides a base exponent from which to determine the exponent of the final number.
The underflow/overflow circuitry includes a comparator that receives from the ALU the exponent created according to the offset value. The comparator compares the resulting exponent value with the maximum and minimum exponent values allowable in the exponent bit field. If the resulting exponent value is between the maximum and minimum values, the comparator outputs a signal to the modify circuitry that results in the modify circuitry conforming the shifted mantissa and adjusted exponent to the IEEE standard and outputting the conformed result. However, if the resulting exponent is smaller than the minimum exponent value, the comparator provides a flag signaling an underflow. Similarly, if the resulting exponent is greater than the maximum exponent value, the comparator produces a flag signaling an overflow.
Although the above underflow/overflow detection scheme operates adequately, it suffers from the disadvantage of slowing the operation of floating point units. The use of comparator circuitry in a separate step increases the time necessary to complete an arithmetic operation by at least one clock cycle for each operation performed. Thus, because floating point units iteratively perform multiple operations, the comparator circuitry significantly increases the time required to complete a series of operations.
The separate step of underflow/overflow detection not only undesirably slows floating point unit performance, but it also precludes the use of such floating point units with high speed circuitry. For example, circuitry operating at high frequencies would require a result from a floating point unit at a time before an operation has been finished. That is, the additional clock cycles required to perform the extra underflow/overflow detection step slows the floating point unit to a level where it cannot perform arithmetic operations fast enough to satisfy the demands of high speed circuitry.
Accordingly, circuitry that eliminates the separate step of underflow/overflow detection would significantly increase the speed of any floating point unit so that it could be utilized with high speed circuitry.